l Both analog-to-digital converter (ADC)s and the digital-toanalog converter (DAC) support sample rates of 8, 16, 32, 44.1, 48, 96 kHz. The DAC also supports 192 kHz.

Peripherals and physical interfaces

l A UART interface

l 2 x Bit Serializers (programmable serial peripheral interface (SPI) and I²C hardware accelerator)

l 1 x USB interface:

n A full speed USB (USB-FS) Device (12 Mbps) – USB interface includes ESD protection to IEC-61000-4-2 (device level)

l QSPI NOR flash interface

n QSPI encryption to protect developer code and data

n Encryption programmable with a 128‑bit security key of original equipment manufacturer (OEM) choice stored in on-chip one-time programmable (OTP) memory

l Up to 15 PIO and 5 open drain/digital input LED pads with pulse width modulation (PWM)

l BM5124 has a secure digital input/output (SDIO) v2.0 compliant Host with 1 port, capable of interfacing to storage device (SD), or multimedia card (MMC) cards

System Architecture

Package information

To download the package layout design: https://share.weiyun.com/5LZIHPq

Package dimensions

BM3024, BM3034 and BM5124 module is available an 18.00 x 11.90 x 2.75mm 52-lead package

Pinout diagram

Module Terminal Functions

USB	Lead	Pad type	Description
USB_DP	8	Bidirectional	USB data plus with selectable internal 1.5kΩ pull-up resistor
USB_DN	7	Bidirectional	USB data minus

PIO Port	Lead	Pad type	Description
AIO	LED Pin	Bidirectional	Analog programmable input line 0
PIO[0]	24	Bidirectional with strong pull-up	Programmable input/output line 0 UART_RX: UART data input
PIO[01]	31	Bidirectional with strong pull-up	Programmable input/output line 1 UART_TX: UART data output
PIO[02]	30	Bidirectional with weak pull-down	Programmable input/output line 2 SPI_MOSI: Debug SPI data input I2S1_SD_IN: I2S 1 synchronous data input SPDIF_IN: SPDIF input
PIO[03]	25	Bidirectional with weak pull-down	Programmable input/output line 3 SPI_MISO: Debug SPI data output I2S1_SD_OUT: I2S 1 synchronous data output
PIO[04]	24	Bidirectional with weak pull-down	Programmable input/output line 4 SPI_CS#: chip select for debug SPI, active low I2S1_WS: I2S 1 word select
PIO[05]	27	Bidirectional with weak pull-down	Programmable input/output line 5 SPI_CLK: Debug SPI clock I2S1_SCK: I2S 1 synchronous data clock
PIO[06]	26	Bidirectional with strong pull-down	Programmable input/output line 6 I2S2_SD_OUT: I2S 2 synchronous data output
PIO[07]	29	Bidirectional with strong pull-down	Programmable input/output line 7 I2S2_WS: I2S 2 word select
PIO[08]	28	Bidirectional with strong pull-up	Programmable input/output line 8 UART_RTS: UART request to send, active low I2S2_SD_IN: I2S 2 synchronous data input
PIO[15]	5	Bidirectional with strong pull-down	Programmable input/output line 9 UART_CTS: UART clear to send, active low I2S2_SCK: I2S 2 synchronous data clock
PIO[16]	4	Bidirectional with strong pull-up	Programmable input/output line 16
PIO[17]	3	Bidirectional with strong pull-down	Programmable input/output line 17
PIO[18]	2	Bidirectional with weak pull-down	Programmable input/output line 18
PIO[19]	1	Bidirectional with weak pull-down	Programmable input/output line 21

Codec	Lead	Pad type	Description
SPKR_LP	36	Analog out	Speaker output positive, left
SPKR_LN	35	Analog out	Speaker output negative, left
SPKR_RP	34	Analog out	Speaker output positive, right
SPKR_RN	33	Analog out	Speaker output negative, right
MIC_BIAS	38	Analog in	Microphone bias
MIC1_P	42	Analog in	Line input positive, channel B
MIC1_N	41	Analog in	Line input negative, channel B
MIC2_P	40	Analog in	Line or microphone input positive, A
MIC2_N	39	Analog in	Line or microphone input negative, A

LED drivers / AIO	Lead	Pad type	Description
LED[0]	15	Bidirectional	Open-drain output
LED[1]	16	Bidirectional	Open-drain output
LED[2]	17	Bidirectional	Open-drain output
LED[4]	18	Bidirectional	Open-drain output
LED[5]	19	Bidirectional	Open-drain output

Power supplies and control	Lead	Description
VBAT	12	Battery positive terminal
VCHG_SENSE	10	Battery charger sense input
VCHG	14	Charger input, typically connected to USB VBUS
CHG_EXT	11	External battery charger transistor base control when using external charger boost. Otherwise leave unconnected
VOUT_1V8	21	1.8V by pass linear regulator output.
POWER (VREGENABLE)		Regulator enable and multifunction button. A high input (tolerant to VBAT voltages) enables the on-chip regulators, which can then be latched on internally and the button used as a multifunction input
GND	6,13,20,32,37,43,45	Ground connections

Technical Specifications

General Specification

Items	Description
Bluetooth Standard	Bluetooth v5.0 and v5.1 Specification support Bluetooth Low Energy secure connection
Chipset	Qualcomm QCC3024, QCC3034, QCC5124
Dimension	18.00 x 11.90 x 2.75mm 52-lead package
Frequency Range	2402～2480MHz
Bluetooth® Profile Supported	A2DP v1.3.1 AVRCP v1.6 HFP v1.7 HSP V1.2 SPP V1.2 DID V1.3 HOGP V1.0 PXP V1.0.1 FMP V1.0 BAS V1.0

Electrical Characteristics

Absolute Maximum Rating

Parameter	Pin	Min	Max	Unit
Storage temperature	-	-40	85	°C
Supply voltage
5 V (USB VBUS)	CHG_EXT	-0.4	7.0	V
	LX_1V8
	LX_DIG
	SMPS_DCPL
	SMPS_VCHG
	VCHG_SENSE
	VDD_BYP_CHG
Battery	SMPS_VBAT	-0.4	4.8	V
	VBAT
	VBAT_SENSE
3.3 V	USB_DN	-0.4	3.8	V
	USB_DP
	VDD_BYP
1.8 V	AUDIO_BGBYP	-0.4	2.1	V
	AUDIO_DACREF
	AUDIO_MIC_BIAS
	AUDIO_MIC1_N/ LINEIN_L_N
	AUDIO_MIC1_P/ LINEIN_L_P
	AUDIO_MIC2_N/ LINEIN_R_N
	AUDIO_MIC2_P/ LINEIN_R_P
	VDD_AUDIO_1V8
	VDD_AUDIO_HP_SPKL
	VDD_AUDIO_HP_SPKR
	VDD_AUX
	VDD_BT_1V8
	VDD_PMU_VINDIG
	VDD_XTAL_1V8
1.8 V	AUDIO_HPL_N/ SPKL_N	-0.4	2.1	V
	AUDIO_HPL_P/ SPKL_P
	AUDIO_HPR_N/ SPKR_N
	AUDIO_HPR_P/ SPKR_P
Digital I/O	PIO[61:60, 54:52, 21:15, 8:2]	-0.4	3.8	V

Recommended Operating Conditions

Parameter	Pin	Min	Typ	Max	Unit
Operating temperature range	-	-40	20	85	°C
Supply voltage
5 V (USB VBUS)	CHG_EXT	4.75 / 4.0a	5.0	6.5	V
	SMPS_VCHG
	VCHG_SENSE
	VDD_BYP_CHG
	SMPS_DCPL	2.8	3.7 / 5.0	6.5	V
	LX_1V8	0	3.7 / 5.0	6.5	V
	LX_DIG
Battery	SMPS_VBAT	3.0 / 2.8b	3.7	4.6	V
	VBAT
	VBAT_SENSE
3.3 V	VDD_BYP	2.8	2.9 / 3.3	3.5	V
	USB_DN	0	-	3.6	V
	USB_DP
1.8 V	VDD_AUDIO_1V8	1.7	1.8	1.95	V
	VDD_AUDIO_HP_SPKL
	VDD_AUDIO_HP_SPKR
	VDD_AUX
	VDD_BT_1V8
	VDD_PMU_VINDIG
	VDD_XTAL_1V8
	AUDIO_BGBYP	0	-	1.95	V
	AUDIO_DACREF
	AUDIO_MIC_BIAS
	AUDIO_MIC1_N/ LINEIN_L_N
	AUDIO_MIC1_P/ LINEIN_L_P
	AUDIO_MIC2_N/ LINEIN_R_N
	AUDIO_MIC2_P/ LINEIN_R_P
1.8 V	AUDIO_HPL_N/ SPKL_N	0	-	1.95	V
	AUDIO_HPL_P/ SPKL_P
	AUDIO_HPR_N/ SPKR_N
	AUDIO_HPR_P/ SPKR_P
Digital I/O	VDD_PADS_7:1	1.7	1.8	3.6	V
	PIO[61:60, 54:52, 21:15, 8:2]	0	-	VDD_PADS	V

Battery input pin specification

VBAT	Min	Typ	Max	Unit
Operating voltage	2.8	3.7	4.6	V
Software power-off threshold	-	3	-	V
Under voltage lockout rising threshold	2.47	2.6	2.73	V
Under voltage lockout hysteresis	50	-	120	mV
USB dead/weak battery rising threshold	3.14	3.3	3.46	V
USB dead/weak battery hysteresis	50	-	120	mV

Charger input pin specification

VCHG	Min	Typ	Max	Unit
Operating voltage (full device specification)	4.75	5	6.5	V
Operating voltage (reduced charger specification)	4.0	5	6.5	V
VCHG_PRESENT rising threshold	3.4	3.6	4.0	V
VCHG_PRESENT hysteresis	70	-	150	mV
Full operating range	VCHG_ PRESENT	-	6.5	V
On chip pull-down (disabled when VCHG_PRESENT = 1)	10	20	30	kΩ

Bypass LDO

	Min	Typ	Max	Unit
Input voltage	VDD_BYP_BAT / VDD_BYP_CHG			V
Output voltage, operating from VDD_BYP_CHG, >0.3 V headroom	3.2	3.3	3.4	V
Output voltage, operating from VDD_BYP_BAT, >0.3 V headroom	2.8	2.9	3	V
Pass device resistance when headroom <0.3 V	-	-	6	Ω
Output current	-	-	50	mA
Current available for external use	-	-	25	mA
ULP modea
Output voltage, operating from VDD_BYP_CHG	3.1	3.3	3.5	V
Output voltage, operating from VDD_BYP_BAT	2.7	2.9	3.1	V
Maximum load current	-	-	1	mA

Digital terminals

	Min	Typ	Max	Unit
VDD_PADS supply	1.7	1.8	3.6	V
VIL input logic level low	-	-	0.22 x VDD_PADS	V
VIH input logic level high	0.7 x VDD_PADS	-	-	V
Drive current (configurable)	2, 4, 8, 12	4	-	mA
VOL output logic level low, at max rated drive	-	-	0.22 x VDD_PADS	V
VOH output logic level high, at max rated drive	0.75 x VDD_PADS	-	-	V
Strong pull (up & down)	15	65	150	kΩ
Weak pull (up & down)	500	2200	5000	kΩ

LED driver

LED driver pads		Min	Typ	Max	Unit
Open drain current	High impedance state	-	-	5	µA
Open drain current	Current sink state	-	-	50	mA
LED pad resistance	V < 0.5 V	-	-	12	Ω
VIL input logic level low		-	-	0.4	V
VIH input logic level high		1.0	-	-	V

ESD protection

Test	Pins	Specification	Class
Human Body Model	AIO/LED [5:4, 2:0]	JS-001-2017	1C (1000 V)
Human Body Model	All other pins	JS-001-2017	2 (2000 V)
Charge Device model	All pins	JS-002-2014	C2a (500 V)
System Level ESD	■ USB_DN	IEC 61000‑4‑2 (device level)	Level 4 (8 kV contact / 15 kV air)
	■ USB_DP
	■ AUDIO_MIC1_N/ LINEIN_L_N
	■ AUDIO_MIC1_P/ LINEIN_L_P
	■ AUDIO_MIC2_N/ LINEIN_R_N
	■ AUDIO_MIC2_P/ LINEIN_R_P

Power Consumption

BM3034	Item	Min	Type	Max	Unit	Note
State	Working voltage	3.0	3.3	4.6	V
	Working current	6	8	10	mA	Call and Music
	Standby current		500		uA
Power supply: 3.3V

Audio performance

Class-D DAC audio output

Parameter	Conditions	Min	Typ	Max	Unit
Input Sample Width	-	-	-	24	Bits
Input Sample Rate, Fsample	-	8	-	192	kHz
Max Power	0 dBFS, 32 Ω, and 16 Ω load	-	-	30	mW
Load	-	16	32	30k	Ω
SNR	fin = 1 kHz 48 kHz Fsample B/W = 20 Hz → 20 kHz A-Weighted -1 dBFS 32 Ω load	-	98.3	-	dBA
THD+N	fin = 1 kHz 48 kHz B/W = 20 Hz → 20 kHz 0 dBFS 30 mW 32 Ω load	-	-87.5	-	dB
Digital gain	Digital gain resolution = 1/32	-24	-	21.5	dB
Stereo separation (crosstalk)	-	80	-	-	dB

Class-AB DAC audio output

Parameter	Conditions	Min	Typ	Max	Unit
Input Sample Width	-	-	-	24	Bits
Input Sample Rate, Fsample	-	8	-	192	kHz
Max Power	0 dBFS, 32 Ω, and 16 Ω load	-	-	30	mW
Load	-	16	32	30k	Ω
SNR	fin = 1 kHz 48 kHz Fsample B/W = 20 Hz → 20 kHz A-Weighted -1 dBFS 32 Ω load	-	101	-	dBA
THD+N	fin = 1 kHz 48 kHz B/W = 20 Hz → 20 kHz 0 dBFS 30 mW 32 Ω load	-	-90.5	-	dB
Digital gain	Digital gain resolution = 1/32	-24	-	21.5	dB
Stereo separation (crosstalk)	-	80	-	-	dB

High-quality (HQADC) single-ended audio input

Parameter	Conditions	Min	Typ	Max	Unit
Output Sample Width	-	-	-	24	Bits
Output Sample Rate, Fsample	-	8	-	96	kHz
Input level	-	-	-	2.4	V pk-pk
Input impedance	0 dB to 24 dB analog gain	-	20	-	kΩ
Input impedance	27 dB to 39 dB analog gain	-	10	-	kΩ
SNR	fin = 1 kHz 48 kHz A-Weighted THD+N<0.1% 2.4 V pk-pk input (0 dB gain)	-	101	-	dBA
THD+N	fin = 1 kHz 48 kHz 2.4 V pk-pk input (0 dB gain)	-	-85	-	dB
Digital gain	Digital gain resolution = 1/32	-24	-	21.5	dB
Analog gain	3 dB steps	0	-	39	dB
Stereo separation (crosstalk)	-	80	-	-	dB

High-quality (HQADC) differential audio input

Parameter	Conditions	Min	Typ	Max	Unit
Output Sample Width	-	-	-	24	Bits
Output Sample Rate, Fsample	-	8	-	96	kHz
Input level	-	-	-	2.4	V pk-pk
Input impedance	0 dB to 24 dB analog gain	-	20	-	kΩ
Input impedance	27 dB to 39 dB analog gain	-	10	-	kΩ
SNR	fin = 1 kHz 48 kHz A-Weighted THD+N<0.1% 2.4 V pk-pk input (0 dB gain)	-	100	-	dBA
THD+N	fin = 1 kHz 48 kHz 2.4 V pk-pk input (0 dB gain)	-	-91	-	dB
Digital gain	Digital gain resolution = 1/32	-24	-	21.5	dB
Analog gain	3 dB steps	0	-	39	dB
Stereo separation (crosstalk)	-	80	-	-	dB

Microphone bias

Parameter	Conditions	Min	Typ	Max	Unit
Output voltage (Tunable, step = 0.1 V)	-	1.5	-	2.1	V
Output current capability	-	0.07	-	3.0	mA
Output noise	B/W = 20 Hz → 20 kHz Unweighted	4.5	5.1	7.3	μVrms
Crosstalk Between Microphones	Using recommended application circuit	-	80	-	dB

Reference Design

To download the reference design or other informations: https://share.weiyun.com/5LZIHPq

Related recommended

l Module output audio is differential signal

l If you want to use the MIC function, order to achieved the best sound effects, please don’t tack MIC and SPK is placed in the same plane, preferably vertically placed.

l Full metal shell will greatly shorten the Bluetooth transmission distance

l Bluetooth antenna below PCB plate not copper

Reference SMT Temperature Monitoring

Pre-heat 150-190°C	Pre-heat 190-220°C	Peak temp	Time above 220°C
55 s	25 s	235-240°C	45 s

Reflow

Soak time (150–190°C): 60–70 s (Solder paste dependent) Ramp time (190–220°C): 20–25 s

Peak temperature (minimum 245°C): Temperature measured on body of part

Time above liquidus: 45–70 s

The use of Nitrogen is recommended to assist solder wetting

A. Ensure that the soak and ramp times are not excessively long, or the solder balls may re-oxidize before liquidus and result in non-wets between the PCB and the package.

l This area should be the focus of the SMT process of non-PoP and pre-stacked PoP assembly

B. Ensure the ramp time and time above liquidus (TAL) are sufficiently long enough to wet the solder joints between the MSM device and memory.

l This area should be the focus for the pre-stack reflow process

Document history

Version	Data	History
1.0	April 18, 2018	The First Release Version
1.1	May 18, 2018	Update Audio Performance
1.2	July 20, 2019	Combine BM3024, 3034 and 5124 datasheet together

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